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HV758 Quad High Speed 90V 2.2A Ultrasound Pulser
Features
HVCMOS technology for high performance High density integration ultrasound transmitter 0 to 90V output voltage 2.2A source and sink current in PW mode 580mA source and sink current in CW mode Up to 20MHz operating frequency Matched delay times 1.2V to 5.0V CMOS logic interface Built-in output drain bleed resistors
General Description
The Supertex HV758 is a four-channel, monolithic high voltage, high-speed pulse generator. It is designed for medical ultrasound applications. This high voltage and high-speed integrated circuit can also be used for other piezoelectric, capacitive or MEMS transducers in ultrasonic nondestructive detection and sonar ranger applications. The HV758 comprises a controller logic interface circuit, level translators, MOSFET gate drives and high current power Pchannel and N-channel MOSFETs as the output stage for each channel. The output current limit can be set to one of four levels by using two mode control inputs. The output stages of each channel are designed to provide peak output currents over 2.5A when in mode 4, with up to 180V swings. When in mode 1, the output stages reduce the peak current to 580mA for CW mode operation, which reduces the power dissipation of the IC. The power MOSFET gate drivers are supplied by two floating 10VDC power supplies referenced to VPP and VNN. This direct coupling topology of the gate drivers not only saves two high voltage capacitors per channel, but also makes the PCB layout easier.
Application
Medical ultrasound imaging Piezoelectric transducer drivers NDT ultrasound transmission Pulse waveform generator
Typical Application Circuit
+1.8 to 3.3V C1 VLL OTP EN MC0 MC1 PIN1 +1.8 to 3.3V Logic NIN1 Level Translator N-Driver RN1 RGND VNN C7 VNN +10V C6 0 to -90V TXN1
EN_PWR
+10V C2 VDD C3
+90V VPP -10V C4 VSUB
SUB
0 to +90V C5 VPP
VPF
RGND RP1
Level Translator
P-Driver
TXP1
D1 HVOUT1 D2
X1
1 of 4 Channels
GREF
VSS
HV758
VNF
HV758
Ordering Information
Package Options Device HV758 64-Ball FCBGA 8x8mm body, 2.45mm height (max), 0.8mm pitch HV758FB HV758FB-G
-G indicates package is RoHS compliant (`Green')
Absolute Maximum Ratings
Parameter VSS, Power supply reference VLL, Positive logic supply VDD, Positive logic and level translator supply (VPP - VPF) Positive floating gate drive supply (VNF - VNN) Negative gate floating drive supply (VPP - VNN) Differential high voltage supply VPP, High voltage positive supply VNN, High voltage negative supply OTP, Over Temperature Protection output All logic input PINX, NINX and EN voltages (VSUB - VPP) Substrate to VPP voltage difference (VPP - TXPX) VPP to TXPX voltage difference (VSUB - TXPX) Substrate to TXPX voltage difference (TXNX - VNN ) TXNX to VNN voltage difference Operating temperature Storage temperature Thermal resistance, JA, (4 layer, 1oz., 4x3", 36-via PCB) Value 0V -0.5V to +7.0V -0.5V to +14V -0.5V to +14V -0.5V to +14V
Pin Configuration
1 A B C D E 2 3 4 5 6 7 8
+190V -0.5V to +95V +0.5V to -95V -0.5V to +7.0V -0.5V to +7.0V +190V +190V +190V +190V -40C to +125C -65C to +150C 12.8C/W
YYWW HV758FB LLLLLLLLL
F G H
64-Ball FCBGA
(top view)
Package Marking
YY = Year Sealed WW = Week Sealed L = Lot Number = "Green" Packaging
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground.
64-Ball FCBGA
Power-Up Sequence
1 2 3 4 5 6 VSUB VLL with logic signal low VDD (VPP - VPF) and (VNF - VNN) VPP and VNN Logic control signals
Power-Down Sequence
1 2 3 4 5 6 All logic signals go to low VPP and VNN (VPP - VPF) and (VNF - VNN) VDD VLL VSUB
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HV758
Operating Supply Voltages and Current (4 Channel Active)
(Operating conditions, unless otherwise specified, VSS = 0V, VLL = +3.3V, VDD = +10V, VPP-VPF = +10V, VNN-VNF = -10V, VPP =+90V, VNN = -90V, TA = 25C)
Symbol Parameter VLL VDD VPF VNF VSUB VPP VNN SRmax ILL IDDQ IDDEN IDDEN IDDENCW IPPQ IPPEN IPPENCW INNQ INNEN INNENCW IPFQ IPFEN IPFENCW INFQ INFEN INFENCW Logic voltage reference Internal voltage supply Positive gate driver supply Negative gate drive supply IC substrate voltage Positive HV supply Negative HV supply Allowable slew rate on VPP, VNN VLL Current EN = Low VDD Current EN = Low VDD Current EN = High VDD Current MODE = 4 VDD Current MODE = 1 VPP Current EN = Low VPP Current MODE = 4 VPP Current MODE = 1 VNN Current EN = Low VNN Current MODE = 4 VNN Current MODE = 1 VPF Current EN = Low VPF Current MODE = 4 VPF Current MODE = 1 VNF Current EN = Low VNF Current MODE = 4 VNF Current MODE = 1
Min 1.2 7.5 (VPP-12.6) (VNN+7.5) VDD 0 -90 -
Typ 2.5 12 (VPP-12)
Max 5.0 12.6 (VPP-7.5)
Units Conditions V V V V V V V V/s A A mA mA mA A mA mA A mA mA A mA mA A mA mA ----Floating driver voltage supplies equals VDD. Must be the most positive potential of the IC. ----------f = 0MHz f = 5.0MHz, continuous, no loads f = 0MHz f = 5.0MHz, continuous, no loads f = 0MHz f = 5.0MHz, continuous, no loads f = 0MHz f = 5.0MHz, continuous, no loads f = 0MHz f = 5.0MHz, continuous, no loads
(VNN+12) (VNN+12.6) VPP 125 100 1.1 3.2 3.1 74 258 215 78 258 215 37 70 9.0 35 42 6.0 +90 +90 0 25 250 2.0 90 90 70 70 -
Note: All supply current values are for reference only.
Under Voltage and Over Temperature Protection
Symbol Parameter VPULL_UP Open drain pull-up voltage VUVDD VUVLL VUVVF VOL_OTP IOTP TOTP THYS VDD threshold VLL threshold VPF, VNF threshold OTP flag output low voltage Max. open drain output current Over-temperature threshold OTP output reset hysteresis Min 3.5 0.8 2.7 95 Typ 5.7 0.9 4.0 1.0 110 7.0 Max 5.0 7.0 1.0 5.4 1.0 125 Units Conditions V V V V V mA C --------VLL = 2.5V, OTP = Active, IPULL_UP = 1.0mA. --If over-temperature occurred, OTP low and all TX outputs will be HiZ.
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HV758
Electrical Characteristics
(Operating conditions, unless otherwise specified, VSS = 0V, VLL = +3.3V, VDD = +10V, VPP-VPF = +10V, VNN-VNF = -10V, VPP =+90V, VNN = -90V, TA = 25C)
Output P-Channel MOSFET, TXP (Mode 4)
Symbol Parameter IOUT RON COSS Output saturation current Channel resistance Output capacitance Min 2.2 Typ 2.5 11 215 Max Units Conditions A pF --ISD = 100mA VDS = 25V, f = 1.0MHz
Output N-Channel MOSFET, TXN (Mode 4)
Symbol Parameter IOUT RON COSS Output saturation current Channel resistance Output capacitance Min 2.1 Typ 2.2 11 90 Max Units Conditions A pF --ISD = 100mA VDS = 25V, f = 1.0MHz
MOSFET Drain Bleed Resistor
Symbol Parameter RP/N1~4 PRO Output bleed resistance Bleed resistors power limit Min 10 Typ 15 Max 20 40 Units Conditions k mW -----
Logic Inputs
Symbol Parameter VIH VIL IIH IIL CIN Input logic high voltage Input logic low voltage Input logic high current Input logic low current Input logic capacitance Min (VLL-0.4) 0 -10 Typ Max VLL 0.4 10 5.0 Units Conditions V V A A pF -----------
AC Electrical Characteristics
Symbol Parameter tr tf fOUT HD2 tEN tdr tdf tdm tDELAY tj Output rise time Output fall time Output frequency range Second harmonic distortion Enable time Delay time on inputs rise Delay time on inputs fall Delay on mode change Itdr-tdfI delay time matching Delay jitter on rise or fall
(Operating conditions, unless otherwise specified, VSS = 0V, VLL = +3.3V, VDD = +10V, VPP-VPF = +10V, VNN-VNF = -10V, VPP =+90V, VNN = -90V, TA = 25C)
Min 20 -
Typ 32 32 30 70 18 18 2.5 15
Max 250 20 3.0 -
Units Conditions ns ns MHz dB s ns ns s ns ps P to N, channel to channel VPP/VNN = +/-25V, input tr 50% to HVOUT tr or tf 50%, with 330pF//2.5k load 100 resistor load 330pF//2.5k load
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HV758
Switching Time Diagram
NINx
50% PINx tdr 90%
50% tdf VPP
Output
10% tr
tf 0 10%
VNN
90%
Truth Table (All Modes)
Logic Inputs EN 1 1 1 1 0
*Note: Not allowed, may damage IC
Output NINX 0 0 1 1 X TXPX OFF ON OFF ON* OFF TXNX OFF OFF ON ON* OFF
PINX 0 1 0 1 X
Drive Mode Control Table
Mode 1 2 3 4 MC1 0 0 1 1 MC0 0 1 0 1 ISC
(A)
RONP
()
RONR
()
0.58 0.8 1.35 2.5
28 20 12 6.5
27 19.7 11.7 6.3
Notes: 1.VPP/VNN = +/-90V, VDD = (VPP - VPF) = (VNF - VNN) = +10V 2. ISC is current into 1.0 to GND 3. RON calculated from VOUT into 100 load
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HV758
Ball Description
Name VDD VSS VLL GREF VSUB RGND VPP VNN VPF VNF TXP1 TXN1 TXP2 TXN2 TXP3 TXN3 TXP4 TXN4 PIN1 NIN1 PIN2 NIN2 PIN3 NIN3 PIN4 NIN4 EN MC0, MC1 OTP Function Positive internal voltage supply (+10V). Power supply return (0V). Logic Hi voltage reference input (+3.3V). Logic Low reference, logic ground (0V). Substrate of the IC, all VSUB pins must connect externally to the most positive potential of the IC. Bleed resistors common return ground. Positive high voltage power supply (+90V). Negative high voltage power supply (-90V). P-FET drive floating power supply, (VPP - VPF) = +10V. N-FET drive floating power supply, (VNF - VNN) = +10V. Output P-FET drain (open drain output) for channel 1. Output N-FET drain (open drain output) for channel 1. Output P-FET drain (open drain output) for channel 2. Output N-FET drain (open drain output) for channel 2. Output P-FET drain (open drain output) for channel 3. Output N-FET drain (open drain output) for channel 3. Output P-FET drain (open drain output) for channel 4. Output N-FET drain (open drain output) for channel 4. Input logic control of high voltage output P-FET of channel 1, Hi=on, Low=off. Input logic control of high voltage output N-FET of channel 1, Hi=on, Low=off. Input logic control of high voltage output P-FET of channel 2, Hi=on, Low=off. Input logic control of high voltage output N-FET of channel 2, Hi=on, Low=off. Input logic control of high voltage output P-FET of channel 3, Hi=on, Low=off. Input logic control of high voltage output N-FET of channel 3, Hi=on, Low=off. Input logic control of high voltage output P-FET of channel 4, Hi=on, Low=off. Input logic control of high voltage output N-FET of channel 4, Hi=on, Low=off. Chip power enable Hi=on, Low=off. Output current mode control pins, see Drive Mode Control Table. Over temperature protection output, open N-FET drain, active low if IC temperature >110C.
Ball Configuration
A1 Corner A B C D E F G H 1 VPF VPF VDD VSS VSS VDD VPF VPF 2 VPP VPP VSUB OTP VLL VSUB VPP VPP 3 VPP VPP PIN4 PIN3 PIN2 PIN1 VPP VPP 4 VNN VNN NIN4 NIN3 NIN2 NIN1 VNN VNN 5 VNN VNN MC0 MC1 EN GREF VNN VNN 6 VNF VNF VSUB RGND RGND VSUB VNF VNF 7 TXN4 TXP4 TXN3 TXP3 TXN2 TXP2 TXN1 TXP1 8 TXN4 TXP4 TXN3 TXP3 TXN2 TXP2 TXN1 TXP1
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HV758
64-Ball FCBGA Package Outline (FB)
8x8mm body, 2.45mm height (max.), 0.80mm pitch
E 8 7 6 5 4 3 2 1 A e B Note 1 (Index Area D/4 x E/4) C D D1 E SD F G H e SE E1 D
Top View
Bottom View
Detail A A Seating Plane b
A2
A1
Side View
Detail A
Note 1: Ball A1 identifier must be located in the index area indicated. Ball A1 corner identification can be used by ink or by metalized markings, or other features on package body. Shape of identifier is optional.
Symbol
A
A1
A2
b
D
D1
E
E1
e
SD
SE
MIN Dimension (mm) NOM MAX
Drawings are not to scale.
1.67 1.82 2.45
0.25 0.40 0.45
1.32 1.42 2.20
0.45 0.50 0.55
7.85 8.00 8.15 5.60 BSC
7.85 8.00 8.15 5.60 BSC 0.80 BSC 0.40 BSC 0.40 BSC
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to http://www.supertex.com/packaging.html.)
Doc.# DSFP-HV758 NR061807
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